Thesis supervisor: Zoltán Attila Godó
Location of studies (in Hungarian): University of Debrecen Faculty of Informatics Abbreviation of location of studies: DE IK
Description of the research topic:
While neural networks -such as AI developments- are software models relying on the analogy of the nervous system, hardware-based neural networks represent actual parallel systems and are closer to the architecture of the living nervous system, providing quite novel solutions.
In this research, we will develop a microcontroller-based multiprocessor (currently 216 processors) parallel analogue/digital neural network (ADNC). We will develop both the hardware - digital
electronics and software aspects of this. For this we are developing a completely novel 3D software visualisation and hardware LED visualisation. On the resulting system, we will investigate parallel solutions to different problems.
Arbitrary real parallel software solutions can be implemented on the system. Thus, we welcome applications for a separate PhD thesis:
- Hardware and/or software development of a multiprocessor neural network
- 3D visualisation of the real-time operation of the neural network
- Modelling the nervous system of simple living organisms and controlling an robot as a body analogue through an artificial neural network
- Investigating the skills of students in algorithm building and parallel programming paradigms in artificial neural network representation
- Development of modelling of other parallel processes
Varga Mátyás, Soltész Bence, Fiedler Norbert Béla, Apró Anikó, Borsos Balázs, Kiss Gábor, Godó Zoltán A., „Neuron Network Model in the Study of Smart City Ideas” Proceedings of the 1st Conference on Information Technology and Data Science CITDS 2020) Debrecen, Magyarország: CEUR Workshop Proceedings (2021) pp. 270-278. , 9 p.
S. Furber, S. Temple, and A. Brown, "On-chip and inter-chip networks for modelling large-scale neural systems," in Proc. International Symposium on Circuits and Systems, ISCAS-2006, Kos, Greece, May 2006.
P. Dayan and L. Abbott, Theoretical Neuroscience. Cambridge: MIT Press, 2001.
S. B. Furber, S. Temple, and A. D. Brown, "High-performance computing for systems of spiking neurons," in AISB'06 workshop on GC5: Architecture of Brain and Mind, vol. 2, Bristol, April 2006, pp. 29-36.
S. Furber and S. Temple, "Neural Systems Engineering," J. R. Soc. Interface, vol. 4, no. 13, pp. 193-206, Apr. 2007.
A. Rast, S. Yang, M. Khan, and S. Furber, "Virtual synaptic interconnect using an asynchronous network-on-chip," in Proc. 2008 Int'l Joint Conf. on Neural Networks (IJCNN2008), 2008.
X. Jin, S. Furber, and J. Woods, "Efficient modelling of spiking neural networks on a scalable chip multiprocessor," in Proc. 2008 Int'l Joint Conf. on Neural Networks (IJCNN2008), 2008.
L. A. Plana, S. B. Furber, S. Temple, M. Khan, Y. Shi, J. Wu, and S. Yang, "A. GALS Infrastructure for a Massively Parallel Multiprocessor, " IEEE Design & Test of Computers, vol. 24, no. 5, pp. 454-463, Sept.-Oct. 2007.
H. Markram and M. Tsodyks, "Redistribution of Synaptic Efficacy Between. Neocortical Pyramidal Neurons," Nature, no. 382, pp. 807-810, 1996.
S. Crook, G. Ermentrout, M. Vanier, and J. Bower, "The role of axonal delay in the synchronization of networks of coupled cortical oscillators," J. Computational Neuroscience, vol. 4, no. 2, Apr. 1997.
F. Tuffy, L. McDaid, M. McGinnity, J. Santos, P. Kelly, V. W. Kwan, and J. Alderman, "A time-multiplexing architecture for inter-neuron communications," in Proc. 2006 Int'l Conf. Artificial Neural Networks (ICANN 2006), 2006, pp. 944-952.
Deadline for application: 2024-05-15
2024. IV. 17. ODT ülés Az ODT következő ülésére 2024. június 14-én, pénteken 10.00 órakor kerül sor a Semmelweis Egyetem Szenátusi termében (Bp. Üllői út 26. I. emelet).
Login
